CSPs (chip scale packages) have to date predominantly been constructed on prefabricated substrate strips. In accordance with known CSP technologies based on a substrate, such as Tessera μBGA (micro ball grid array), for example, the rewiring (redistribution lines) or at least parts thereof are already integrated into the prefabricated substrate. Such a rewiring present on the substrate is then contact-connected by means of bonding wires or TAB bonding to an integrated circuit or a chip. The production of the substrate requires complicated and expensive process steps which increase the costs for the substrate. Furthermore, the production and the subsequent process steps are effected with a low degree of parallelism, e.g. in panels or strips with fewer than 150 chips. Both causes have hitherto prevented a further lowering of the production costs of CSPs. Fan-out rewirings can also be generated by means of CSP technologies based on a substrate, for example by means of the BGA technology.
Wafer level package technologies (WLP) likewise provide a cost-effective technology for producing chip scale packages (CSPs), but without being able to provide fan-out rewirings. The wafer level package technologies utilize as a basis the front end wafer, on which the thin-film technique is used in order to produce the fan-in rewiring, the insulation layers, such as e.g. a solder resist layer, and the solder balls. Although the technology steps used in this case for metallization, i.e. sputtering and electrodeposition, for structure production, i.e. photolithography, and for producing protection layers, i.e. spin coating, are cost-intensive, the individual costs per chip can be kept low on account of the high degree of parallelism (entire wafer with up to 1000 chips). In addition, in the future more cost-effective printing technologies will increasingly replace the expensive photolithographic process steps. New printing technologies will make it possible to produce a mask technique using the printing method, which can be used for the highly accurate contact connection of contact pads on a wafer, typical contact pad spacings comprising 130 μm, for example, and typical pad openings comprising 60 μm. Printing processes can thus be used for structure production of rewiring devices or insulation wires on a new panel. However, the WLP production cannot be used to produce fan-out rewirings, i.e. rewirings which project beyond the chip edge.